1. Field of the Invention
This invention is related to the field of processors and, more particularly, to handling misaligned memory operations in processors.
2. Description of the Related Art
Processors generally include support for memory operations to facilitate transfer of data between the processors and memory to which the processors may be coupled. As used herein, a memory operation is an operation specifying a transfer of data between a processor and a main memory (although the transfer may be completed in cache). Load memory operations specify a transfer of data from memory to the processor, and store memory operations specify a transfer of data from the processor to memory. Memory operations may be an implicit part of an instruction which includes a memory operation, or may be explicit load/store instructions. Load memory operations may be more succinctly referred to herein as “loads”. Similarly, store memory operations may be more succinctly referred to as “stores”.
A given memory operation may specify the transfer of multiple bytes beginning at a memory address calculated during execution of the memory operation. For example, 16 bit (2 byte), 32 bit (4 byte), and 64 bit (8 byte) transfers are common in addition to an 8 bit (1 byte) transfer. The address is typically calculated by adding one or more address operands specified by the memory operation to generate an effective address or virtual address, which may optionally be translated through an address translation mechanism to a physical address of a memory location within the memory. Typically, the address may identify any byte as the first byte to be transferred, and the additional bytes of the multiple byte transfer are contiguous in memory to the first byte and stored at increasing (numerical) memory addresses.
Since any byte may be identified as the first byte, a given memory operation may be misaligned. Various processors may define misalignment in different ways. Misaligned memory operations may, in some cases require additional execution resources (as compared to an aligned memory operation) to complete the access. For example, a processor may implement a cache having cache lines. If one or more of the bytes operated upon by the memory operation are in one cache line and the remaining bytes are in another cache line, two cache lines are accessed to complete the memory operation as opposed to one cache line if the accessed bytes are included within one cache line.
Determination of whether or not a given memory operation is misaligned generally does not occur until the memory operation is executed (during which the address is generated). Correctly allocating resources to perform the memory access (aligned or misaligned) may thus be complex.